Hybrid Sine Function Generation for Low Power Direct Digital Frequency Synthesis

High-resolution low-power Direct Digital Frequency Synthesizers (DDFS) with small chip area are investigated. Lookup tables for sine and cosine yield the leading bits of the amplitudes. A CORDIC interpolation scheme enhances the amplitude precision. Systematic case studies using VHDL – models and synthesis indicate, that optimum LUT/CORDIC ratios can minimize use of power and silicon area. Introduction Direct Digital Frequency Synthesis (DDFS) using Numerically Controlled Oscillators (NCOs) is an indispensable technique for generating reference signals whenever high frequency resolution, fast changes in frequency and phase as well as high spectral purity of the output signal are required. Applications range from instrumentation to modern communication systems, which employ spread-spectrum and phase shift-keying modulation techniques [1,2]. An NCO is a digital computing block that renders digital word sequences in time at a given clock frequency fCLK, which thereafter must be converted into analog signals to serve as an oscillator. As usual, the required digital-to-analog converter (DAC) is not considered in the following. Fig. 1 shows a schematic block diagram of a DDFS – system generating sine – and cosine functions. The overflowing accumulator (phase accumulator, PA) clocked with fCLK, generates the phase value sequence Ω(n). The phase summing block (PSB) performs in – flight phase jumps, and the function generator (FG)